1. Field of the Invention
The present invention relates in general to a semiconductor device, and in particular to a semiconductor device utilizing a vertical surround gate MOSFET (will be referred to as a "V.PHI.T" hereinafter). The invention also relates to a method of manufacturing such a semiconductor device. The invention further relates to an improvement of V.PHI.T.
2. Description of the Background Art
FIG. 114 shows trend of cell sizes of dynamic random access memories (DRAMs). FIG. 114 additionally shows design rules in respective generations. Conventional DRAM cells include, as components, bit lines (BL), word lines (WL), bit line contacts (BK), and storage contacts (SK). Therefore, the cell size, which is expressed with F (feature size) of the following formula, is 8F.sup.2. EQU F (feature size)=r+.alpha.
wherein
F represents a gate width, r represents a minimum line width and .alpha. represents a process margin.
In FIG. 114, the design rule (minimum line width) is simply set to F, and 8F.sup.2 and 4F.sup.2 (hollow and solid circles) are plotted in a superimposed form. As can be seen therefrom, the cells of 8F.sup.2 can form 256M-DRAM at the most. Meanwhile, the cell size of 4F.sup.2 can achieve a DRAM of G-bit generation by following the conventional reduction rule.
The cells of 4F.sup.2 can be formed by arranging vertical transistors at crossings of the bit lines BL and word lines Wl. Based on the above background, various kinds of vertical transistors have been proposed.
FIG. 115 is a cross section of a first prior art, which is a vertical surround gate transistor disclosed in Japanese Patent Laying-Open No. 5-160408 (1993). Referring to FIG. 115, a gate 3 is formed around a column 5 of silicon forming a channel with a gate insulating film 4 therebetween. A source 6a and a drain 6b are connected to silicon column 5.
A significant problem arises in connection with formation of gate electrode 3 forming the word line if the above transistor is applied to a DRAM.
FIG. 116 is a cross section of a semiconductor device showing a process of manufacturing the surround gate transistor shown in FIG. 115. Gate insulating film 4 is formed to cover silicon column 5. Then, polysilicon (3) is deposited to cover silicon column 5 with gate insulating film 4 therebetween. Anisotropic etching is effected on polysilicon (3) to form gate electrode 3 on a side wall of silicon column 5. According to this method, a gate length 1 depends on an anisotropic etching rate of polysilicon (3). Therefore, a variation v of the gate length l is large. According to this method, therefore, it is very difficult to obtain stably the cells of 4F.sup.2.
FIGS. 117 and 118 are cross sections showing steps in a process of manufacturing a vertical surround gate transistor disclosed in Japanese Patent Laying-Open No. 4-282865 (1992).
Referring to FIG. 117, an SiO.sub.2 layer 2a, polysilicon, i.e., word line 3 and an SiO.sub.2 layer 2b are formed in this order on a bit line 26. There is also provided a contact hole 8 penetrating SiO.sub.2 layer 2b, polysilicon 3 and SiO.sub.2 layer 2a. Gate insulating film 4 is formed on the side wall of contact hole 8.
Referring to FIGS. 117 and 118, the side wall of contact hole 8 is covered with polysilicon 5. Polysilicon 5 is divided into a source 6a, a channel 7 and a drain 6b. The transistor thus constructed has the following problem. Referring to FIG. 117, variation v of etching quantity is liable to occur when forming gate insulating film 4, and in some cases, an upper corner 3c of the gate electrode is exposed, resulting in leak between corner 3c of the gate and drain 6b.
The transistor also has the following problem in connection with its operation.
The conductivity types of the gate polysilicon and channel polysilicon are opposite to each other, and a difference in their work function is utilized for depleting the channel polysilicon, whereby the off state is achieved between the source and drain. For this purpose, a film thickness of the channel polysilicon must be smaller than the maximum width of the depletion layer which depends on concentration of impurity in the channel polysilicon.
Meanwhile, if the resistance of source/drain is high, a sufficient on-current cannot be obtained. Therefore, it is necessary to increase the content of impurity in the channel polysilicon for lowering the resistance. In an ordinary TFT, the content of impurity in the source/drain is 10.sup.20 l/cm.sup.3 at the most. However, if impurity were introduced at the large content of 10.sup.20 /cm.sup.3, the maximum width of depletion layer would be approximately 40 .ANG.. Therefore, due to restriction that the film thickness of the channel polysilicon must be smaller than the above value, it would probably be impossible to achieve stable manufacturing of the transistors without sacrificing characteristics.
In order to overcome the above problems, the inventors and others have proposed a vertical .PHI.-shaped transistor (V.PHI.T) as shown in FIG. 119 (Japanese Patent Laying-Open No. 5-345126 (1993)).
FIG. 119 is a perspective view showing a major portion of a V.PHI.T. FIG. 120 is a cross section of the V.PHI.T.
Referring to these figures, a MOSFET includes a substrate 1. Source region 6a is formed at a main surface of substrate 1. First interlayer insulating film 2a is formed on substrate 1. Gate electrode 3, which has a top surface substantially parallel to the surface of substrate, is formed on first interlayer insulating film 2a. Second interlayer insulating film 2b covering gate electrode 3 is formed on first interlayer insulating film 2a. A surface of source region 6a is partially exposed through a contact hole 19 which penetrates first interlayer insulating film 2a, gate electrode 3 and second interlayer insulating film 2b. Gate insulating film 4 covers the side wall of contact hole 19. In contact hole 19, there is formed a first semiconductor layer 20 of a P-type, which is in contact with a surface 9 of source region 6a and extends from the surface of source region 6a to the same level as a lower surface of gate electrode 3. In contact hole 19, there is also formed a channel semiconductor layer 7, which is in contact with a surface of first semiconductor layer 20 and extends from the surface of first semiconductor layer 20 to the same level as an upper surface of gate electrode 3. A second semiconductor layer 5 of the P-type, which is in contact with the surface of channel semiconductor layer 7 and forms drain region 6b, is formed on channel semiconductor layer 7.
A third interlayer insulating film 2c covering drain region 6b is formed on the substrate. Third interlayer insulating film 2c is provided with a connection hole 11a exposing a portion of the surface of drain region 6b. An aluminum electrode 10a is connected to drain region 6b through connection hole 11a.
Although the structure shown in FIGS. 119 and 120 can overcome the problems of the technique shown in FIGS. 115 and 117, the capacitance of a bit line can not be reduced below a restricted extent.